Conventional receivers for high speed serial communication systems may include a clock and data recovery circuit that extracts clock and data information from a received serial signal. For example, such a circuit may produce a clock signal synchronized with the incoming signal and the clock signal may then be used to recover data (e.g., data symbols) from the signal. Typically, the clock signal is generated at a frequency that matches the frequency of a data symbol rate in the received signal. The clock signal is then used to sample the received signal to recover individual data bits that correspond to each data symbol.
A clock and data recovery circuit may comprise a phase lock loop or delay lock loop that aligns the edges, for example the rising edges, of a generated clock signal with the transition edges (e.g., the edges of data symbols) of the received signal. As a result, the falling edges of the clock may be generated at times that coincide with approximately the middle of the data symbols. Thus, the falling edges of the clock signal may be used to sample the received signal in the middle of the data symbols.
To effectively extract the clock and data from the received signal, the receiver first makes a decision as to the value (e.g., “+1” or “−1,” “0” or “1,” etc.) represented by each bit of the received data. In a typical receiver that processes non-return-to-zero (“NRZ”) data, the incoming NRZ data is passed through a slicer that determines whether the incoming bit is, for example, a “+1” or a “−1.”
In some applications the slicer may make this determination based on a threshold associated with the signal. For example, the slicer may compare the incoming data with a threshold. Alternatively, the slicer may significantly amplify the signal to generate a signal that is more like a rail-to-rail signal. In this case, the slicer may thereby effectively cause the slicing decision to be made at or near the mid amplitude (e.g., ½ the signal swing) of the signal.
For a signal to be represented by a “+1” or a “−1,” the portion of the signal that is higher than the associated threshold is output by the slicer as a “+1” and the portion of the signal that is lower than the associated threshold is output as a “−1.” Typically, the value of the associated threshold is set to zero (half way between “+1” and “−1”). However, to improve the receiver performance the threshold may be made adjustable.
Some conventional receivers adjust threshold based on a bit error rate (“BER”) analysis of the data recovered by the receiver. This process may involve, for example, sending known test data to the receiver and determining the resulting bit error rate. The threshold level may then be adjusted to provide a lower bit error rate, if possible. Such techniques, however, may require that the receiver include forward error correction (“FEC”) circuitry or other relatively complex circuitry to calculate the bit error rate. In many applications, such additional circuitry may be undesirable. Hence, a need exists for improved techniques for determining an optimum value of a threshold associated with a signal.